1. Technical Field
Embodiments described herein generally relate to processors. In particular, embodiments described herein generally relate to accessing registers in processors.
2. Background Information
Many processors have Single Instruction, Multiple Data (SIMD) architectures. In SIMD architectures, a packed data instruction, vector instruction, or SIMD instruction may operate on multiple data elements or multiple pairs of data elements simultaneously or in parallel. The processor may have parallel execution hardware responsive to the packed data instruction to perform the multiple operations simultaneously or in parallel.
Multiple data elements may be packed within one register or memory location as packed data. In packed data, the bits of the register or other storage location may be logically divided into a sequence of data elements. For example, a 128-bit wide packed data register may have two 64-bit wide data elements, four 32-bit data elements, eight 16-bit data elements, etc.
In some processor architectures, there has been an increase over the years in the width of packed data operands used by instructions. Such increased packed data widths generally allow more data elements to be processed concurrently or in parallel, which tends to improve performance. Even though there are instructions that utilize the wider packed data operands, it is still generally desirable to support the older instructions that utilize the narrower packed data operands, for example to provide backward compatibility. Moreover, often narrower registers that are used to store the narrower packed data operands may be aliased on wider registers that are used to store the wider or expanded packed data operands.